1. Technical Field
The present invention relates to network line equalizers having high-pass filters for equalizing attenuated transmitted analog signals, such as multiple layer transition (MLT-3) decoded signals, from a network medium such as a 100-BASE-TX Ethernet (IEEE standard 802.3u) transmission medium.
2. Background Art
Local area networks use a network cable or other network media to link nodes (e.g., workstations, routers and switches) to the network. Each local area network architecture uses a media access control (MAC) enabling a network interface device at each network node to share access to the media.
Physical (PHY) layer devices are configured for translating digital packet data received from a MAC across a standardized interface, e.g., a media independent interface (Mll), into an analog signal for transmission on the network medium, and reception of analog signals transmitted from a remote node via the network medium. An example is the 100 BASE-TX IEEE standard 802.3u receiver, configured for receiving a 3-level MLT-3 encoded analog signal at a 125 Mb/s data rate.
One problem with transmission of analog signals on the network medium is the attenuation of high-frequency components. For example, FIG. 1A is a diagram illustrating the frequency response characteristics f(line) of the network medium. As shown in FIG. 1A, an MLT-3 encoded signal transmitted by the network medium encounters transmission loss in the form of high-frequency attenuation. Hence, the 100-BASE-TX Ethernet (IEEE 802.3u) receiver includes a line equalizer having a high-pass filter, having the frequency response (f (filter)) of FIG. 1B to compensate for the high-frequency attenuation from the network medium. One example of a high-pass filter is a single zero filter.
FIG. 2 is a diagram illustrating a conventional single zero high-pass filter 10. As shown in FIG. 2, the high-pass filter 10 includes an operational amplifier 12, a capacitor 14 having capacitance C, and a resister 16 having resistance R. As recognized in the art, the high-pass filter 10 has a transfer function H(s)=S+Z, where Z equals 1/RC. Hence, the high-pass circuit 10 is considered a single zero filter, where S is a complex variable based on frequency.
A disadvantage of the high pass filter 10 is that a high bandwidth operational amplifier 12 is required for implementation. In addition, a direct connection of the high-pass filter 10 within a line equalizer may affect the impedance of the transmission line (i.e., the network medium), since the capacitor 14 and resistor 16 are in parallel with the transmission line""s termination resistance. In addition, the connection of the capacitor 14 is between the two nodes (VIN and VO), neither of which is a ground or a supply node. Hence, the high-pass filter 10 is extremely difficult to implement using CMOS technology, since a CMOS capacitor cannot be connected between two arbitrary nodes.
There is a need for an arrangement that enables a single zero high-pass to be implemented using CMOS technology with minimal effort.
There is also a need for an arrangement for providing a single zero high-pass filter using MOS transistors that provides a single zero filtering with minimal complexity.
There is also a need for an arrangement in a network line equalizer, where a high-pass filter includes a single zero impedance circuit that has an impedance that can be selectable by a control signal.
These and other needs are attained by the present invention, where first and second metal oxide semiconductor (MOS) transistors, each having a gate for receiving a corresponding differential input signal, are connected to a single zero impedance circuit for generation of differential currents and/or voltages based on the impedance and the differential input signals.
According to one aspect of the present invention, a single zero high-pass filter includes first and second metal oxide semiconductor (MOS) transistors, each having a gate for receiving a corresponding differential input signal, and first and second junctions, and a single zero impedance circuit connecting the first and second MOS transistors at the corresponding first junctions, wherein the second junctions of the first and second MOS transistors output respective differential currents having a difference corresponding to the impedance and the differential input signals. Use of the MOS transistors for receiving the differential input signals provide an infinite DC impedance to the input terminals, significantly reducing signal attenuation at the inputs receiving the differential input signals. Moreover, the MOS transistors provide a high speed operation due to the direct and simple conversion of input voltage between the differential input signals into operating current, where the first and second MOS transistor act as source followers. The use of the MOS transistor also results in an extremely simple high-pass filter that requires little area on a semiconductor circuit. The single zero impedance circuit also enables MOS gate capacitance to be used as at least part of the capacitance element of the impedance, advantageous for CMOS processes where the capacitance element with arbitrary node connection is not available, as opposed to node-to-ground or node to-Vcc only.
Another aspect of the present invention includes a network line equalizer configured for receiving a differential pair of transmitted signals from a network medium and outputting a corrected differential pair of transmitted signals. The network line equalizer includes a high-pass filter including (1) first and second MOS transistors, each having a gate for receiving the corresponding differential transmitted signal, and (2) a single zero impedance circuit having an impedance selectable by a control signal. The single zero impedance circuit connects the first and second MOS transistors, and causes the first and second MOS transistors to output the corrected differential pair of transmitted signals based on the impedance. The network line equalizer also includes a control outputting the control signal for selecting the impedance. The selectable impedance in the single zero impedance circuit enables the equalizer to be easily tuned to compensate for different frequency response characteristics, enabling the line to compensate for attention due to different length network media. The use of MOS transistors increases the bandwidth of the line equalizer, enabling CMOS technology to be used. Moreover, the connection of the single zero impedance circuit to the MOS transistor eliminates the necessity of a feedback loop, enabling the line equalizer to perform line equalization for high-frequency signals, without introducing any stability problems.
Still another aspect of the present invention provides a method of equalizing a differential pair of input signals received from a network medium. The method comprises supplying the differential pair of input signals to gates of first and second MOS transistors, respectively, the first and second MOS transistors each having a first junction and a second junction, selecting an impedance of a single zero impedance circuit having first and second terminal ends connected to the first junctions of the first and second MOS transistors, respectively, and outputting a differential pair of equalized signals, generated based on the differential pair of input signals and the selected impedance, from the second junction of the first and second MOS transistors, respectively. Use of a single zero impedance circuit having an impedance selectable by a control signal enables a controller to select the impedance, for example based on changes in the line characteristics of the network media supplying the transmitted signals to the network line equalizer. Moreover, use of first and second MOS transistors for receiving the differential transmitted signal increases the input bandwidth of the high-pass filter, and increases the input resistance of the line equalizer to minimize distortion in the signal received by the network line equalizer.
Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part may become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.